This invention relates to an adjustable ratio divider.
Adjustable ratio dividers are commonly used in phase locked loop circuits to divide a signal fed from a controllable oscillator to a phase comparator. Changing the division of the divider changes the frequency of the oscillator and this oscillator provides an output frequency.
It is desirable to produce the phase locked loop circuit in integrated circuit form and in particular as a single chip.
The production of a phase locked loop circuit in a single chip leads to conflicting requirements. It is desirable to keep power consumption in the frequency dividers, particularly the adjustable ratio divider, as low as possible and this means that the dividers should operate at a relatively low frequency.
A relatively low frequency is not, however, ideal for phase comparison and for better acquisition time of the loop and lower ripple in the output frequency, a maximised reference frequency is desired. Also for high frequency operation e.g. a frequency range extending through the loop down from about 1 GH.sub.z, the higher frequency portion of the loop must be formed in high frequency logic such as ECL (emitter coupled logic).
ECL logic is not compact compared with a lower frequency logic such as Integrated Injection Logic (I.sup.2 L) and extensive use of ECL would result in an undesirably large chip.